P-type or N-type doped polycrystalline silicon (hereinafter referred to as “polysilicon”) is generally employed as a gate electrode material for the gate electrode of a MOS transistor. When the gate is formed over a P-type well (i.e., the source and drain are formed with N-type dopants), the resulting structure is referred to as an N-channel MOS (NMOS) structure. In digital applications, NMOS transistors and PMOS transistors are commonly formed on adjacent regions of an integrated circuit. This complementary MOS structure is commonly referred to as a CMOS structure. The drains of the two complementary transistors are connected together and form the output, while the input terminal is the common connection to the transistor gate. CMOS transistors offer the advantages of low power consumption, low operation voltage, high degree of integration, and high noise margin.
CMOS fabrication techniques may be classified into various categories according to the manner in which the gate electrode is formed. Among them, the dual gate technique has widely been used, since the elements incorporated into the device are integrated to a high degree and minimized to increase voltage characteristics and operating speed. In the dual gate technique, P-type and N-type impurities are implanted into respective polysilicon gates of corresponding impurity type transistors. Dual gate type CMOS semiconductor devices offer the advantages of reinforcement of the surface layer portions of the channels and enablement of symmetrical lower voltage operation.
In the fabrication of high performance dual gate type CMOS semiconductor devices, boron is commonly used as a dopant that is doped or implanted into a polysilicon gate layer to form a gate. Usually, doping of the polysilicon gate is carried out concurrently with the implanting of impurities into the semiconductor substrate to form source/drain regions.
However, implanted boron is not uniformly distributed into the polysilicon gate. Namely, the polysilicon gate does not have a uniform doping profile. For example, a portion of the polysilicon gate that neighbors the gate insulating layer (i.e., the lower portion of the polysilicon gate) has a lower doping level than other portions. Furthermore, implanted boron penetrates the thin gate insulating layer and diffuses into the semiconductor substrate (referred to as “boron penetration”). Particularly, boron penetration can be severe in a PMOS transistor having a very thin gate insulating layer on the order of dozens of angstroms. Boron penetration causes variation in the threshold voltage of the semiconductor device. Furthermore, the lower doping level of boron in the lower portion of the polysilicon gate causes a depletion region to form (referred to as “gate polysilicon depletion”) when voltage is applied to the gate during operation. Gate polysilicon depletion results in incremental destruction of the equivalent gage insulating layer.
In order to address the issues of boron depletion and gate polysilicon depletion, silicon-germanium (Si-Ge) has become popular for use as a gate material in CMOS-type semiconductor devices. Since germanium offers a higher degree of solubility for boron as compared to conventional polysilicon, boron has a uniform doping profile throughout the silicon-germanium gate, and thus, the possibility of boron out-diffusion (boron penetration) into the channel region is very low.
A silicon-germanium gate is useful in a PMOS transistor for blocking boron penetration and gate polysilicon depletion. However, this does not apply well to the NMOS transistor. Indeed, an NMOS transistor with N-type doped silicon-germanium gate has worse characteristics than NMOS transistor with N-type doped silicon gate without germanium. The use of an N-type silicon-germanium gate in an NMOS transistor carries with it a number of significant disadvantages. N-type dopants such as arsenic and phosphorus that are added to the silicon-germanium gate are difficult to activate, and are easily deactivated again through heating during subsequent manufacturing treatments at elevated temperatures. These non-activated atoms of the dopant give rise to undesired strong depletion of the gate polysilicon.
On the other hand, during a silicon fabrication process using a refractory metal for lowering gate contact resistance, germanium blocks the interaction between polysilicon and the refractory metal in the PMOS transistor. Accordingly, there is a strong need for a new CMOS fabrication technique without the above-described drawbacks.